1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a fine electrode or wiring pattern made of polycrystalline silicon.
2. Description of the Related Art
Conventionally, a method such as illustrated in FIGS.8 to 10 has been proposed in forming a gate electrode of polycrystalline silicon (polysilicon) in a MOS type LSI or the like.
Referring to FIG.8, the surface of a semiconductor substrate 10 made of silicon is oxidized to form a gate insulating film 12 made of silicon oxide. Thereafter, a polysilicon layer 14 is deposited on the insulating film 12 by means of a chemical vapor deposition method (CVD) or the like. N-type impurities P are doped in the polysilicon layer 14 to lower the resistance of the polysilicon layer 14, by a diffusion process using gas such as O.sub.2 +POCl.sub.3. During this diffusion process, a silicon oxide film including impurity oxide (such as P.sub.2 O.sub.5) is formed on the surface of the polysilicon layer 14. This silicon oxide film is removed by an etching process.
Thereafter, a resist pattern 15 corresponding to a desired gate electrode pattern is formed on the surface of the polysilicon layer 14. Using the resist pattern is as a mask, the polysilicon layer 14 is selectively etched by means of a dry etching process using HBr or Cl.sub.2 as etchant, to leave a gate electrode layer 14A.
Referring next to FIG.9, an ashing process using O.sub.2 gas and a washing process using H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 are performed to remove the resist pattern 15. In this case, peripheral layers 15a and 15b of the resist pattern 15 are left unremoved, the components of those layers having been altered by etching gas or reaction by-products. The component-altered layers 15a and 15b are removed by an HF process as illustrated in FIG.10. In this manner, a polysilicon gate electrode of a MOS transistor is formed.
Another method of forming a gate electrode has been proposed as illustrated in FIGS.13 to 15. Like elements to those shown in FIGS.8 to 10 are represented by using identical reference numerals.
Referring to FIG.13, the processes up to the process of removing a silicon oxide film on the polysilicon layer 14 formed during the impurity doping process are the same as those described with FIG.8. Thereafter, a silicon oxide film 17 is formed on the polysilicon layer 14 by means of a CVD method or the like. Then, a resist pattern 19 corresponding to a desired gate electrode pattern is formed on the film 17.
Referring next to FIG.14, using the resist pattern 19 as a mask, the silicon oxide film 17 is selectively and anisotropically etched to leave an oxide etching mask 17A. Thereafter, the resist pattern 19 is removed.
Referring next to FIG.15, using the oxide etching mask 17a, the polysilicon layer 14 is selectively dry-etched to leave a gate electrode layer 14A.
With the method explained with FIGS.8 to 10, during the polysilicon etching process shown in FIG.8, carbon (C) emerges from the organic compound resist pattern 15. Therefore, even if HBr or Cl.sub.2 not containing C is used as etchant, the etching selection ratio of polysilicon to SiO.sub.2 lowers (for example, refer to the monthly magazine "Semiconductor World", January issue, 1990, pp.81 to 84). From this reason, the thickness of the gate insulating film 12 made of SiO.sub.2 reduces.
Further, the component-altered layers 15a and 15b shown in FIG.9 are left unavoidably if gas not containing C or F such as HBr or Cl.sub.2 is used for the polysilicon etching. An HF process described with FIG.10 is therefore required in order to remove such component-altered layers. This HF process may reduce thickness of the gate insulating film 12 made of silicon oxide during the HF process.
Furthermore, as shown in FIG.11, in the case where resist layers 15A and 15B are deposited abreast on a polysilicon layer 14 to be etched, with the space W between the resist layers being set smaller than the thickness T of the resist layers, the aspect ratio T/W becomes larger. In this case, the etching speed for the polysilicon layer at the narrow space area becomes different from that at a broad area (or near an isolated pattern line), presenting a so-called micro loading effect which an etching rate varies depending upon a ratio of area of mask aperture to the entire area or upon local pattern density off the mask aperture.
For example, as shown in FIG. 12, consider the case where lines 14a and 14b with a narrow space therebetween are formed by etching the polysilicon layer 14 using the resist layers 15A and 15B as a mask. If the etching speed at the narrow space area is greater than other broad areas because of the micro loading effect, the gate insulating film 12 and/or the substrate surface may sometimes be etched partially. If the etching is suppressed to avoid this over-etching, the polysilicon at the narrow space area may sometimes be left unetched and the lines 14a and 14b are short-circuited. In such a case, the manufacturing yield and reliability are lowered.
With the method explained with FIGS.13 to 15, on the other hand, the following disadvantages are present: (a) a CVD process or the like is required to deposit a silicon oxide film, complicating the manufacturing process, and (b) the manufacturing yield may be lowered by particles because a CVD process produces relatively many particles.